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56852
Data Sheet Technical Data
56800E 16-bit Digital Signal Controllers
DSP56852 Rev. 8 01/2007
freescale.com
DSP56852 General Description
* 120 MIPS at 120MHz * 6K x 16-bit Program SRAM * 4K x 16-bit Data SRAM * 1K x 16-bit Boot ROM * 21 External Memory Address lines, 16 data lines and four chip selects * One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) * One (1) Serial Communication Interface (SCI) * Interrupt Controller * General Purpose 16-bit Quad Timer * JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging * Computer Operating Properly (COP)/Watchdog Timer * 81-pin MAPBGA package * Up to 11 GPIO
6
VDDIO 6
VDD 3
VSSIO 6
VSS VDDA 3
VSSA
JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit
16-Bit 56800E Core
Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit
PAB PDB CDBR CDBW
Memory
Program Memory 6144 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 4096 x 16 SRAM
R/W Control
XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
System Bus Control
System Address Decoder
System Device
IPBus Bridge (IPBB)
RW Control IPAB IPWDB IPRDB
Peripheral Address Decoder
Decoding Peripherals
A0-16 A17-18 muxed (timer pins) A19 muxed (CS3) D0-D12[12:0] D13-15 muxed (Mode A,B,C) WR Enable RD Enable CS[2:0] muxed (GPIOA) External Address Bus Switch External Data Bus Switch External Bus Interface Unit
Peripheral Device Selects
Clock resets
P O R
PLL
SCI or GPIOE
Bus Control
1 Quad Timer or A17, A18
SSI or SPI or GPIOC
COP/ Watchdog
Interrupt Controller
System Integration Module
Clock Generator
O S C
XTAL EXTAL
2
2
6 IRQA IRQB
3 CLKO RESET muxed (A20) MODE muxed (D13-15)
56852 Block Diagram
56852 Technical Data, Rev. 8 Freescale Semiconductor 3
Part 1 Overview
1.1 56852 Features
1.1.1
* * * * * * * * * * * * * * * *
Core
Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three (3) internal address buses and one (1) external address bus Four (4) internal data buses and one (1) external data bus Instruction set supports both DSP and controller functions Four (4) hardware interrupt levels Five (5) software interrupt levels Controller-style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced OnCE debug programming interface
1.1.2
* *
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory On-chip memory includes: -- 6K x 16-bit Program SRAM -- 4K x 16-bit Data SRAM -- 1K x 16-bit Boot ROM 21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals
*
1.1.3
* * * * * * * *
Peripheral Circuits for DSP56852
General Purpose 16-bit Quad Timer with two external pins* One (1) Serial Communication Interface (SCI)* One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module* Interrupt Controller Computer Operating Properly (COP)/Watchdog Timer JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging 81-pin MAPBGA package Up to 11 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
56852 Technical Data, Rev. 8 4 Freescale Semiconductor
56852 Description
1.1.4
* *
Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs Wait and Stop modes available
1.2 56852 Description
The 56852 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56852 is well-suited for many applications. The 56852 includes many peripherals especially useful for low-end Internet appliance applications and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote metering; and sonic alarms. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C-Compilers, enabling rapid development of optimized control applications. The 56852 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56852 also provides two external dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56852 includes 6K words of Program RAM, 4K words of Data RAM and 1K of Boot RAM. It also supports program execution from external memory. This controller also provides a full set of standard programmable peripherals that include one improved Synchronous Serial Interface (SSI) or one Serial Peripheral Interface (SPI), one Serial Communications Interface (SCI), and one Quad Timer. The SSI, SPI, SCI I/O and three chip selects can be used as General Purpose Input/Outputs when its primary function is not required. The SSI and SPI share I/O, so, at most, one of these two peripherals can be in use at any time.
1.3 State of the Art Development Environment
* * Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
56852 Technical Data, Rev. 8 Freescale Semiconductor 5
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description of and proper design with the 56852. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 DSP56852 Chip Documentation
Topic DSP56800E Reference Manual DSP56852 User's Manual DSP56852 Technical Data Sheet DSP56852 Errata Description Detailed description of the 56800E architecture, 16-bit controller core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56852 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number DSP56800ERM DSP56852UM DSP56852 DSP56852E
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR "asserted" "deasserted" Examples:
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56852 Technical Data, Rev. 8 6 Freescale Semiconductor
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56852 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or signals present. Table 2-1 Functional Group Pin Allocations
Functional Group Power (VDD, VDDIO, or VDDA) Ground (VSS, VSSIO,or VSSA) Phase Lock Loop (PLL) and Clock External Bus Signals External Chip Select* Interrupt and Program Control Synchronous Serial Interface (SSI) Port* Serial Communications Interface (SCI) Port* Serial Peripheral Interface (SPI) Port Quad Timer Module Port JTAG/Enhanced On-Chip Emulation (EOnCE) *Alternately, GPIO pins
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. CLKOUT is muxed Address pin A20. 3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins. 4. CS3 is multiplexed with external Address Bus pin A19. 5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18. 6. Four of these pins are multiplexed with SSI. 7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.
Number of Pins 101 101 22 393 34 35 6 2 06 07 6
56852 Technical Data, Rev. 8 Freescale Semiconductor 7
Logic Power
VDD VSS
3 3
1 1
RXD(GPIOE0) TXD(GPIOE1) SCI
I/O Power
VDDIO VSSIO
6 6
1 1 1 1
GPIOC0(STXD) GPIOC1(SRXD) SCLK(GPIOC2)(STCK) SS(GPIOC3)(STFS) MISO(GPIOC4)(SRCK) MOSI(GPIOC5)(SRFS) SPI SSI
Analog Power1
VDDA VSSA
1 1
1 1
56852
A0-16 A17(TI/O) Address Bus A18(TI/O) A19(CS3) CLKO(A20) 17 1 1 1 1 1 1
IRQA IRQB
Interrupt Request
1 1
XTAL EXTAL Oscillator
1 GPIOA0(CS0) Chip Select GPIOA1(CS1) GPIOA2(CS2) 1 1 1 1 1 Data Bus D0-D12 D13-D15/MODEA-C 13 3 1 1 1 1 RD Bus Control WR 1 1
RESET
Reset
TCK TDI TDO TMS TRST DE JTAG/Enhanced OnCE
Figure 2-1 56852 Signals Identified by Functional Group
56852 Technical Data, Rev. 8 8 Freescale Semiconductor
Introduction
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. Mode pins D13, D14 and D15 have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Ouput(Z) means an output in a High-Z condition.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA
Pin No. E1 J5 E9 D1 J4 F9 C1 H1 J7 G9 B9 A4 B1 G1 J6 J9 C9 A5 B5 B6 Signal Name VDD VDD VDD VSS VSS VSS VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VDDA VSSA VDDA VSSA Analog Power--These pins supply an analog power source Analog Ground--This pin supplies an analog ground. VSSIO I/O Power - GND--These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS. VDDIO I/O Power --These pins provide power for all I/O and ESD structures of the chip, and should all be attached to VDDIO. VSS Logic Power - GND--These pins provide grounding for the internal structures of the chip and should all be attached to VSS. Type VDD Description Logic Power --These pins provide power to the internal structures of the chip, and should all be attached to VDD.
56852 Technical Data, Rev. 8 Freescale Semiconductor 9
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No. E4 F2 F3 F4 F1 G3 G2 J1 H2 H3 J2 H4 G4 J3 F5 H5 E5 F6 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 TIO0 G5 A18 TIO1 H6 A19 CS3 Output(Z) Input/Output Output(Z) Input/Output Output(Z) Output Address Bus (A17) Timer I/O (0)--Can be programmed as either a timer input source or as a timer output flag. Address Bus (A18) Timer I/O (1)--Can be programmed as either a timer input source or as a timer output flag. Address Bus (A19) External Chip Select 3 --When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Output clock (CLKO)--User programmable clock out reference Address Bus--A20 Chip Select 0 (CS0) --When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (0) --A general purpose IO pin. Type Output(Z) Description Address Bus (A0-A16)--These pins specify a word address for external program or data memory addresses.
J8
CLKO A20
Output Output Output
D2
CS0
GPIOA0
Input/Output
56852 Technical Data, Rev. 8 10 Freescale Semiconductor
Introduction
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No. D3 Signal Name CS1 Type Output Description Chip Select 1 (CS1) --When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (1) --A general purpose IO pin. Chip Select 2 (CS2)--When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (2) --A general purpose IO pin. Data Bus (D0-D12) --specify the data for external program or data memory accesses. D0-D15 are tri-stated when the external bus is inactive.
GPIOA1 C3 CS2
Input/Output Output
GPIOA2 G7 H7 H8 G8 H9 F8 F7 G6 E8 E7 E6 D8 D7 D9 C8 A9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 MODE A D14 MODE B D15 MODE C
Input/Output Input/Output
Input/Output
Data Bus (D13-D15) -- specify the data for external program or data memory accesses. D0-D15 are tri-stated when the external bus is inactive. Mode Select--During the bootstrap process the MODE A, MODE B, and MODE C pins select one of the eight bootstrap modes. These pins are sampled at the end of reset. Note: Any time POR and EXTERNAL resets are active, the state of MODE A, B and C pins get asynchronously transferred to the SIM Control Register [14:12] ($1FFF08) respectively. These bits determine the mode in which the part will boot up. Note: Software and COP resets do not update the SIM Control Register.
E2
RD
Output
Bus Control- Read Enable (RD)--is asserted during external memory read cycles. When RD is asserted low, pins D0-D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the controller. RD can be connected directly to the OE pin of a Static RAM or ROM.
56852 Technical Data, Rev. 8 Freescale Semiconductor 11
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No. E3 Signal Name WR Type Output Description Bus Control-Write Enable (WR)-- is asserted during external memory write cycles. When WR is asserted low, pins D0-D15 become outputs and the controller puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15 pins. WR can be connected directly to the WE pin of a Static RAM. SCI Receive Data (RXD)--This input receives byte-oriented serial data and transfers it to the SCI receive shift register. Port E GPIO (0)--A general purpose I/O pin. SCI Transmit Data (TXD)--This signal transmits data from the SCI transmit data register. Port E GPIO (1)--A general purpose I/O pin. Port C GPIO (0)--This pin is a General Purpose I/O (GPIO) pin when the SSI is not in use. SSI Transmit Data (STXD)--This output pin transmits serial data from the SSI Transmitter Shift Register. Port C GPIO (1)--This pin is a General Purpose I/O (GPIO) pin when the SSI is not in use. SSI Receive Data (SRXD)--This input pin receives serial data and transfers the data to the SSI Receive Shift Register. SPI Serial Clock (SCLK)--In Master mode, this pin serves as an output, clocking slaved listeners. In Slave mode, this pin serves as the data clock input. Port C GPIO (2)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Transfer Clock (STCK)--This bidirectional pin provides the serial bit rate clock for the transmit section of the SSI. The clock signal can be continuous or gated. SPI Slave Select (SS)--In Master mode, this pin is used to arbitrate multiple masters. In Slave mode, this pin is used to select the slave. Port C GPIO (3)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Transfer Frame Sync (STFS) --This bidirectional pin is used to count the number of words in a frame while transmitting. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation.
B4
RXD
Input
GPIOE0 D4 TXD
Input/Output Output(Z)
GPIOE1 B2 GPIOC0
Input/Output Input/Output
STXD A2 GPIOC1
Output Input/Output
SRXD
Input
A3
SCLK
Input/Output
GPIOC2
Input/Output
STCK B3 SS
Input/Output Input
GPIOC3
Input/Output
STFS
Input/Output
56852 Technical Data, Rev. 8 12 Freescale Semiconductor
Introduction
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No. C4 Signal Name MISO Type Input/Output Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port C GPIO (4)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Receive Clock (SRCK)--This bidirectional pin provides the serial bit rate clock for the receive section of the SSI. The clock signal can be continuous or gated. SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port C GPIO (5)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Receive Frame Sync (SRFS)-- This bidirectional pin is used to count the number of words in a frame while receiving. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation. External Interrupt Request A (IRQA)--The IRQA Schmitt trigger input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. External Interrupt Request B (IRQB)--The IRQB Schmitt trigger input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. External Crystal Oscillator Input (EXTAL)--This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. Crystal Oscillator Output (XTAL)--This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input.
GPIOC4
Input/Output
SRCK C5 MOSI
Input/Output Input/ Output (Z)
GPIOC5
Input/Output
SRFS A1 IRQA
Input/Output Input
C2
IRQB
Input
A6
EXTAL
Input
A7
XTAL
Input/Output
56852 Technical Data, Rev. 8 Freescale Semiconductor 13
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No. D5 Signal Name RESET Type Input Description Reset (RESET)--This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial Chip Operating mode is latched from the D[15:13] pins. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST. C6 TCK Input Test Clock Input (TCK)--This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/Enhanced OnCE port. The pin is connected internally to a pull-down resistor. Test Data Input (TDI)--This input pin provides a serial input data stream to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output (TDO)--This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Mode Select Input (TMS)--This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: D6 TRST Input Always tie the TMS pin to VDD through a 2.2K resistor.
B7
TDI
Input
A8
TDO
Output
C7
TMS
Input
Test Reset (TRST)--As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the device. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
B8
DE
Input/Output
Debug Even (DE)-- is an open-drain, bidirectional, active low signal. As an input, it is a means of entering Debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered Debug mode.
56852 Technical Data, Rev. 8 14 Freescale Semiconductor
General Characteristics
Part 4 Specifications
4.1 General Characteristics
The 56852 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56852 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56852 Technical Data, Rev. 8 Freescale Semiconductor 15
Table 4-1 Absolute Maximum Ratings
Characteristic
Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding VDD, VSS, VDDA, VSSA,VDDIO, VSSIO Junction temperature Storage temperature range
1. VDD must not exceed VDDIO 2. VDDIO and VDDA must not differ by more that 0.5V
Symbol
VDD1 VDDIO2 VDDIO2 VIN VINA I
Min
VSS - 0.3 VSSIO - 0.3 VSSA - 0.3 VSSIO - 0.3 VSSA - 0.3 --
Max
VSS + 2.0 VSSIO + 4.0 VDDA + 4.0 VSSIO + 5.5 VDDA + 0.3 10
Unit
V V
V
mA
TJ TSTG
-40 -55
120 150
C C
Table 4-2 Recommended Operating Conditions
Characteristic
Supply voltage for Logic Power Supply voltage for I/O Power Supply voltage for Analog Power Ambient operating temperature PLL clock frequency1 Operating Frequency2 Frequency of peripheral bus Frequency of external clock Frequency of oscillator Frequency of clock via XTAL Frequency of clock via EXTAL
Symbol
VDD VDDIO VDDA TA fpll fop fipb fclk fosc fxtal fextal
Min
1.62 3.0 3.0 -40 -- -- -- -- 2 -- 2
Max
1.98 3.6 3.6 85 240 120 60 240 4 240 4
Unit
V V V C MHz MHz MHz MHz MHz MHz MHz
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz PLL must be enabled, locked, and selected. The actual frequency depends on the source clock frequency and programming of the CGM module. 2. Master clock is derived from one of the following four sources: fclk = fxtal when the source clock is the direct clock to EXAL fclk = fpll when PLL is selected fclk = fosc when the source clock is the crystal oscillator and PLL is not selected fclk = fextal when the source clock is the direct clock to EXAL and PLL is not selected
56852 Technical Data, Rev. 8 16 Freescale Semiconductor
DC Electrical Characteristics
Table 4-3 Thermal Characteristics1
Characteristic
Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed PD
1. See Section 6.1 for more detail. 2. TJ = Junction Temperature TA = Ambient Temperature
81-pin MAPBGA Symbol
JA PI/O PD PDMAX
Value
36.9 User Determined PD = (IDD x VDD) + PI/O (TJ - TA) / RJA2
Unit
C/W W W W
4.2 DC Electrical Characteristics
Table 4-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL < 50pF, fop = 120MHz
Characteristic
Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage Input low voltage Input current low (pullups disabled) Input current high (pullups disabled) Output tri-state current low Output tri-state current high Output High Voltage at IOH Output Low Voltage at IOL Output High Current at VOH Output Low Current at VOL Input capacitance Output capacitance
Symbol
VIHC VILC VIH VIL IIL IIH IOZL IOZH VOH VOL IOH IOL CIN COUT
Min
VDDA - 0.8 -0.3 2.0 -0.3 -1 -1 -10 -10 VDDIO - 0.7 -- 8 8 -- --
Typ
VDDA -- -- -- -- -- -- -- -- -- -- -- 8 12
Max
VDDA + 0.3 0.5 5.5 0.8 1 1 10 10 -- 0.4 16 16 -- --
Unit
V V V V A A A A V V mA mA pF pF
56852 Technical Data, Rev. 8 Freescale Semiconductor 17
Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL < 50pF, fop = 120MHz
Characteristic
VDD supply current (Core logic, memories, peripherals) Run Deep Stop2 Light Stop3 VDDIO supply current (I/O circuity) Run Deep Stop2 VDDA supply current (analog circuity) Deep Stop
2 5 1
Symbol
IDD4
Min
Typ
Max
Unit
-- -- -- IDDIO -- -- IDDA -- VEI VEIH POR -- -- --
55 0.02 3.4
70 2.5 8
mA mA mA
40 0 60 2.5 50 1.5
50 300 120 2.85 -- 2.0
mA A A V mV V
Low Voltage Interrupt6 Low Voltage Interrupt Recovery Hysteresis Power on Reset7
Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out. 1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz. 2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator. 3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator. 4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry. 5. Running core and performing external memory access. Clock at 120 MHz. 6. When VDD drops below VEI max value, an interrupt is generated. 7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.8V, no matter how long the ramp up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
56852 Technical Data, Rev. 8 18 Freescale Semiconductor
Supply Voltage Sequencing and Separation Cautions
150
EMI Mode5 MAC Mode1
120
90
IDD (mA)
60
30
0
20
40
60
80
100
120
Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
DC Power Supply Voltage
3.3V
VDDIO, VDDA 2
Supplies Stable VDD
1.8V
1
0
Note: 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD
Time
Figure 4-2 Supply Voltage Sequencing and Separation Cautions
56852 Technical Data, Rev. 8 Freescale Semiconductor 19
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 2.1V) In practice, VDDA is typically connected directly to VDDIO with some filtering.
3.3V Regulator VDDIO, VDDA
Supply
1.8V Regulator
VDD
Figure 4-3 Example Circuit to Control Supply Sequencing
4.4 AC Electrical Characteristics
Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of VIH and VIL for an input signal are shown.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 4-4 Input Signal Measurement References
56852 Technical Data, Rev. 8 20 Freescale Semiconductor
External Clock Operation
Figure 4-5 shows the definitions of the following signal states:
* * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3
Figure 4-5 Signal States
4.5 External Clock Operation
The 56852 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins.
4.5.1
Crystal Oscillator for Use with PLL
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 2-4MHz (optimized for 4MHz)
EXTAL XTAL Rz
Sample External Crystal Parameters: Rz = 10M TOD_SEL bit in CGM may be set to 0 or 1. 0 is recommended.
Figure 4-6 Crystal Oscillator
56852 Technical Data, Rev. 8 Freescale Semiconductor 21
4.5.2
High Speed External Clock Source (> 4MHz)
The recommended method of connecting an external clock is given in Figure 4-7. The external clock source is connected to XTAL and the EXTAL pin is held at ground (recommended), VDDA, or VDDA/2. The TOD_SEL bit in CGM must be set to 1.
56852 XTAL EXTAL GND,VDDA, External Clock or VDDA/2 (up to 240MHz)
Figure 4-7 Connecting a High Speed External Clock Signal using XTAL
4.5.3
Low Speed External Clock Source (2-4MHz)
The recommended method of connecting an external clock is given in Figure 4-8. The external clock source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM may be set to 0 or 1. 0 is recommended.
56852 XTAL EXTAL External Clock (2-4MHz)
VDDA/2
Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL
Table 4-5 External Clock Operation Timing Requirements4
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Frequency of operation (external clock driver)1 Clock Pulse Width4 External clock input rise time2, 4 External clock input fall time3, 4
Symbol
fosc tPW trise tfall
Min
0 6.25 -- --
Typ
-- -- -- --
Max
240 -- TBD TBD
Unit
MHz ns ns ns
1. See Figure 4-7 for details on using the recommended connection of an external clock driver. 2. External clock input rise time is measured from 10 to 90 percent. 3. External clock input fall time is measured from 90 to 10percent. 4. Parameters listed are guaranteed by design.
56852 Technical Data, Rev. 8 22 Freescale Semiconductor
External Memory Interface Timing
VIH
External Clock
90% 50% 10%
tPW
tPW
90% 50% 10%
tfall
trise
VIL
Note: The midpoint is VIL + (VIH - VIL)/2.
Figure 4-9 External Clock Timing
Table 4-6 PLL Timing
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
External reference crystal frequency for the PLL1 PLL output frequency PLL stabilization time 2
Symbol
fosc fclk tplls
Min
2 40 --
Typ
4 -- 1
Max
4 240 10
Unit
MHz MHz ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. 2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows sample timing and parameters that are detailed in Table 4-7. The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. The equation:
t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in the above equation are defined as: t parameter delay time D fixed portion of the delay, due to on-chip path delays. P the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 MHz, P = 8.33 ns). M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible clock duty cycle derating. W the sum of the applicable wait state controls. See the "Wait State Controls" column of Table 4-7 for the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for details of what each wait state field controls.
56852 Technical Data, Rev. 8 Freescale Semiconductor 23
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating frequency of the part changes. The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. The "Wait States Configuration" column of Table 4-7 should be used to make the appropriate selection.
A0-Axx,CS tRD tARDD tRDA tRDRD
tARDA RD tAWR tWRWR WR tWR tWAC tWRRD
tRDWR
tDWR D0-D15
tDOS
tDOH
tAD
tRDD
tDRD
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 4-10 External Memory Interface Timing
56852 Technical Data, Rev. 8 24 Freescale Semiconductor
External Memory Interface Timing
Table 4-7 External Memory Interface Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, P = 8.333ns
Characteristic
Address Valid to WR Asserted
Symbol
tAWR
Wait States Configuration
WWS=0 WWS>0 WWS=0 WWS>0 WWS=0
D
-0.75 -1.50 -0.52 -0.13 -1.86 - 6.03 -1.73 -4.29 -1.71 -2.38 -4.42 -1.44 - 0.51 -2.03 0.00 -0.97 -10.13 -13.22 - 1.06 -9.06 -12.65 -0.70 -0.172
M
0.50 0.69 0.19 0.00 0.00 0.25 0.19 0.50 0.25 0.19 0.50 0.25 0.00 1.00 N/A1 1.00 1.00 1.19 0.00 1.00 1.19 0.25 0.00 0.75 1.00 0.50 0.69
Wait States Controls
WWSS
Unit
ns
WR Width Asserted to WR Deasserted
tWR
WWS
ns
Data Out Valid to WR Asserted tDWR
WWS=0 WWS>0 WWS>0
WWSS
ns
Valid Data Out Hold Time after WR Deasserted Valid Data Out Set Up Time to WR Deasserted Valid Address after WR Deasserted RD Deasserted to Address Invalid Address Valid to RD Deasserted Valid Input Data Hold after RD Deasserted RD Assertion Width Address Valid to Input Data Valid
tDOH tDOS tWAC tRDA tARDD tDRD tRD tAD tARDA tRDD tWRRD tRDRD tWRWR WWS=0 WWS>0
WWSH WWS,WWSS WWSH RWSH RWSS,RWS -- RWS RWSS,RWS RWSS RWSS,RWS WWSH,RWSS RWSS,RWSH WWSS, WWSH MDAR, BMDAR, RWSH, WWSS
ns ns
ns ns ns ns ns
Address Valid to RD Asserted RD Asserted to Input Data Valid
ns ns ns ns ns
WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted
-0.47 -0.07 0.10 -0.31
RD Deasserted to WR Asserted
tRDWR
ns
1. N/A since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D = 0.00 should be used.
56852 Technical Data, Rev. 8 Freescale Semiconductor 25
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration3 RESET Deassertion to First External Address Output Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 Delay from IRQA Assertion (exiting Stop) to External Data Memory5 Delay from IRQA Assertion (exiting Wait) to External Data Memory Fast6 Normal7 RSTO pulse width8 normal operation internal reset mode
1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL < 50pF, fop = 120MHz
Symbol
tRAZ tRA tRDA tIRW tIDM tIDM -FAST tIG tIG -FAST tIRI tIRI -FAST tIW tIF
Min
-- 30 -- 1T + 3 18T 14T 18T 14T 22T 18T 1.5T
Max
11 -- 120T -- -- -- -- -- -- -- --
Unit
ns ns ns ns ns
See Figure
4-11 4-11 4-11 4-12 4-13
ns
4-13
ns
4-14
ns
4-15 4-15
18T 22ET tRSTO
-- -- -- --
ns ns 4-16
128ET 8ET
-- --
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. 3. At reset, the PLL is disabled and bypassed. The part is then put into run mode and tclk assumes the period of the source clock, txtal, textal or tosc. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. 6. Fast stop mode: Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle and tclk will continue same value it had before stop mode was entered. 7. Normal stop mode: As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate. 8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
56852 Technical Data, Rev. 8 26 Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET tRAZ tRA tRDA
A0-A20, D0-D15 CS, RD, WR
First Fetch
First Fetch
Figure 4-11 Asynchronous Reset Timing
IRQA IRQB
tIRW
Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive)
A0-A20, CS,
RD, WR tIDM
First Interrupt Instruction Execution
IRQA, IRQB a) First Interrupt Instruction Execution
Purpose I/O Pin IRQA, IRQB
tIG
b) General Purpose I/O
Figure 4-13 External Level-Sensitive Interrupt Timing
56852 Technical Data, Rev. 8 Freescale Semiconductor 27
IRQA, IRQB
tIRI
A0-A20, CS, RD, WR
First Interrupt Vector Instruction Fetch
Figure 4-14 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0-A20, CS, RD, WR
First Instruction Fetch Not IRQA Interrupt Vector
Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing
RESET
tRSTO
Figure 4-16 Reset Output Timing
56852 Technical Data, Rev. 8 28 Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
4.8 Serial Peripheral Interface (SPI) Timing
Table 4-9 SPI Timing1
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL < 50pF, fop = 120MHz
Characteristic
Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low time Master Slave Data setup time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave
1. Parameters listed are guaranteed by design.
Symbol
tC
Min
Max
Unit
See Figure
4-17, 4-18, 4-19, 4-20 4-20
25 25 -- 12.5 -- 12.5 9 12.5 12 12.5 10 2 0 2 5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- 15
ns ns ns ns
tELD
tELG
4-20 ns ns ns ns 4-17, 4-18, 4-19, 4-20 4-20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-17, 4-18, 4-19, 4-20 4-17, 4-18, 4-19, 4-20 4-20
tCH
tCL
tDS
tDH
tA
tD tDV
4-20 4-17, 4-18, 4-19, 4-20 4-17, 4-18, 4-19, 4-20 4-17, 4-18, 4-19, 4-20 4-17, 4-18, 4-19, 4-20
2 -- -- 0 0 -- -- -- --
9 2 14 -- -- 11.5 10.0 9.7 9.0
tDI
tR
tF
56852 Technical Data, Rev. 8 Freescale Semiconductor 29
(Input)
SS
SS is held High on master
tC tR tF tCL tCH tF tR
SCLK (CPOL = 0) (Output)
SCLK (CPOL = 1) (Output)
tDS
tCL tDH tCH
tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 4-17 SPI Master Timing (CPHA = 0)
(Input)
SS
tC
SS is held High on master
tF tCL tR
SCLK (CPOL = 0) (Output)
tCH tCL
tF
SCLK (CPOL = 1) (Output)
tCH
tR
tDS tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 4-18 SPI Master Timing (CPHA = 1)
56852 Technical Data, Rev. 8 30 Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
(Input)
SS
tC tCL tELD tCH tCL tR
tF
tELG
SCLK (CPOL = 0) (Input)
SCLK (CPOL = 1) (Input)
tA tCH tR tF tD
MISO (Output)
tDS
Slave MSB out
tDH
Bits 14-1
tDV
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 4-19 SPI Slave Timing (CPHA = 0)
(Input)
SS tF tR tCL tCH tELD tELG tCL tDV tA tCH tF tR tD
tC
SCLK (CPOL = 0) (Input)
SCLK (CPOL = 1) (Input)
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 4-20 SPI Slave Timing (CPHA = 1)
56852 Technical Data, Rev. 8 Freescale Semiconductor 31
4.9 Quad Timer Timing
Table 4-10 Timer Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period
1.
Symbol PIN PINHL POUT POUTHL
Min 2T + 3 1T + 3 2T - 3 1T - 3
Max -- -- -- --
Unit ns ns ns ns
In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 4-21 Timer Timing
56852 Technical Data, Rev. 8 32 Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
4.10 Synchronous Serial Interface (SSI) Timing
Table 4-11 SSI Master Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL < 50pF, fop = 120MHz
Parameter
STCK frequency STCK period3 STCK high time STCK low time Output clock rise/fall time Delay from STCK high to STFS (bl) high - Master4 Delay from STCK high to STFS (wl) high - Master4 Delay from SRCK high to SRFS (bl) high - Master4 Delay from SRCK high to SRFS (wl) high - Master4 Delay from STCK high to STFS (bl) low - Master4 Delay from STCK high to STFS (wl) low - Master4 Delay from SRCK high to SRFS (bl) low - Master4 Delay from SRCK high to SRFS (wl) low - Master4 STCK high to STXD enable from high impedance - Master STCK high to STXD valid - Master STCK high to STXD not valid - Master STCK high to STXD high impedance - Master SRXD Setup time before SRCK low - Master SRXD Hold time after SRCK low - Master
Symbol
fs tSCKW tSCKH tSCKL
Min
Typ
Max
152
Units
MHz ns ns ns
66.7 33.4 33.4 4
ns -0.1 -0.1 1.0 1.0 -0.1 -0.1 0.1 0.1 1 1 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tTFSBHM tTFSWHM tRFSBHM tRFSWHM tTFSBLM tTFSWLM tRFSBLM tRFSWLM tTXEM tTXVM tTXNVM tTXHIM tSM tHM
-1.0 -1.0 0.1 0.1 -1.0 -1.0 -0.1 -0.1 0 0 -0.1 -4 4 4
Synchronous Operation (in addition to standard internal clock parameters) SRXD Setup time before STCK low - Master SRXD Hold time after STCK low - Master
1. Master mode is internally generated clocks and frame syncs
tTSM tTHM
4 4
56852 Technical Data, Rev. 8 Freescale Semiconductor 33
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. bl = bit length; wl = word length
tSCKH STCK output
tSCKW tSCKL
tTFSBHM STFS (bl) output tTFSWHM STFS (wl) output tTXVM tTXEM STXD SRCK output tRFSBHM SRFS (bl) output tRFSWHM SRFS (wl) output First Bit
tTFSBLM
tTFSWLM
tTXNVM Last Bit
tTXHIM
tRFBLM
tRFSWLM
tSM SRXD
tHM
tTSM
tTHM
Figure 4-22 Master Mode Timing Diagram
56852 Technical Data, Rev. 8 34 Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
Table 4-12 SSI Slave Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
STCK frequency STCK period3 STCK high time STCK low time Output clock rise/fall time Delay from STCK high to STFS (bl) high - Slave5 Delay from STCK high to STFS (wl) high - Slave5 Delay from SRCK high to SRFS (bl) high - Slave5 Delay from SRCK high to SRFS (wl) high - Slave5 Delay from STCK high to STFS (bl) low - Slave5 Delay from STCK high to STFS (wl) low - Slave5 Delay from SRCK high to SRFS (bl) low - Slave5 Delay from SRCK high to SRFS (wl) low - Slave5 STCK high to STXD enable from high impedance - Slave STCK high to STXD valid - Slave STFS high to STXD enable from high impedance (first bit) Slave STFS high to STXD valid (first bit) - Slave STCK high to STXD not valid - Slave STCK high to STXD high impedance - Slave SRXD Setup time before SRCK low - Slave
Symbol
fs tSCKW tSCKH tSCKL
Min
Typ
Max
152
Units
MHz ns ns ns
66.7 33.44 33.44 4
ns 29 29 29 29 29 29 29 29 15 15 15 15 15 15 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tTFSBHS tTFSWHS tRFSBHS tRFSWHS tTFSBLS tTFSWLS tRFSBLS tRFSWLS tTXES tTXVS tFTXES tFTXVS tTXNVS tTXHIS tSS
-1 -1 -1 -1 -29 -29 -29 -29 -- 4 4 4 4 4 4
56852 Technical Data, Rev. 8 Freescale Semiconductor 35
Table 4-12 SSI Slave Mode1 Switching Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
SRXD Hold time after SRCK low - Slave
Symbol
tHS
Min
4
Typ
Max
--
Units
ns
Synchronous Operation (in addition to standard external clock parameters) SRXD Setup time before STCK low - Slave SRXD Hold time after STCK low - Slave
1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length
tTSS tTHS
4 4
-- --
? ?
tSCKW tSCKH STCK input tTFSBHS STFS (bl) input tTFSWHS STFS (wl) input tFTXES tTXES STXD SRCK input tRFSBHS SRFS (bl) input tRFSWHS SRFS (wl) input tSS SRXD tHS tTSS tTHS tRFSWLS tTXVS First Bit tFTXVS tTXNVS tTXHIS Last Bit tTFSWLS tTFSBLS tSCKL
tRFSBLS
Figure 4-23 Slave Mode Clock Timing
56852 Technical Data, Rev. 8 36 Freescale Semiconductor
Serial Communication Interface (SCI) Timing
4.11 Serial Communication Interface (SCI) Timing
Table 4-13 SCI Timing4
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width
Symbol BR RXDPW TXDPW
Min -- 0.965/BR 0.965/BR
Max (fMAX)/(32) 1.04/BR 1.04/BR
Unit Mbps ns ns
1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design.
RXD SCI receive data pin (Input)
RXDPW
Figure 4-24 RXD Pulse Width
TXD SCI receive data pin (Input)
TXDPW
Figure 4-25 TXD Pulse Width
MSCAN_RX CAN receive data pin (Input)
T WAKE-UP
Figure 4-26 Bus Wake-up Detection
56852 Technical Data, Rev. 8 Freescale Semiconductor 37
4.12 JTAG Timing
Table 4-14 JTAG Timing1, 3
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time
2
Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE
Min DC 33.3 16.6 3 3 -- -- 35 4T
Max 30 -- -- -- -- 12 10 -- --
Unit MHz ns ns ns ns ns ns ns ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For120MHz operation, T = 8.33 ns 2. TCK frequency of operation must be less than 1/4 the processor rate. 3. Parameters listed are guaranteed by design.
tCY tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 4-27 Test Clock Input Timing Diagram
56852 Technical Data, Rev. 8 38 Freescale Semiconductor
JTAG Timing
TCK (Input) TDI TMS (Input) TDO (Output)
tTS
tDS
tDH
Input Data Valid
tDV
Output Data Valid
TDO (Output)
tDV
TDO (Output)
Output Data Valid
Figure 4-28 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 4-29 TRST Timing Diagram
DE tDE
Figure 4-30 Enhanced OnCE--Debug Event
56852 Technical Data, Rev. 8 Freescale Semiconductor 39
4.13 GPIO Timing
Table 4-15 GPIO Timing
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.7-1.9V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period
Symbol PIN PINHL POUT POUTHL
Min 2T + 3 1T + 3 2T - 3 1T - 3
Max -- -- -- --
Unit ns ns ns ns
GPIO Inputs PIN PINHL PINHL
GPIO Outputs POUT POUTHL POUTHL
Figure 4-31 GPIO Timing
56852 Technical Data, Rev. 8 40 Freescale Semiconductor
GPIO Timing
Part 5 56852 Packaging & Pinout Information
This section contains package and pin-out information for the 81-pin MAPBGA configuration of the 56852.
METALLIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
9
8
7
6
5
4
3
2
1
A
D15 TD0 XTAL
EXTAL
VSSIO
VDDIO
SCK
GPIOC1
IRQA
B
VDDIO DE TDI VSSA VDDA RXD SS
GPIOC0
VSSIO
C
VSSIO D14 TMS TCK MOSI MISO CS2 IRQB VDDIO
D
D13 D11 D12 TRST
RESET
TXD
CS1
CS0
VSS
E
VDD D8 D9 D10 A16 A0 WR RD VDD
F
VSS D5 D6 A17 A14 A3 A2 A1 A4
G
VDDIO D3 D0 D7 A18 A12 A5 A6 VSSIO
H
D4 D2 D1 A19 A15 A11 A9 A8 VDDIO
J
VSSIO CLKO VDDIO VSSIO VDD VSS A13 A10 A7
Figure 5-1 Bottom-View, 56852 81-pin MAPBGA Package
56852 Technical Data, Rev. 8 Freescale Semiconductor 41
Table 5-1 56852 Pin Identification by Pin Number
Pin No. E4 F2 F3 F4 F1 G3 G2 J1 H2 H3 J2 H4 G4 J3 F5 H5 E5 F6 G5 H6 J8 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 CLKO Pin No. D2 D3 C3 G7 H7 H8 G8 H9 F8 F7 G6 E8 E7 E6 D8 D7 D9 C8 A9 B8 Signal Name CS0 CS1 CS2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DE Pin No. A6 B6 D1 J4 F9 B1 G1 J6 J9 C9 A5 A1 C2 C4 C5 B5 E1 J5 E9 C1 Signal Name EXTAL VSSA VSS VSS VSS VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO IRQA IRQB MISO MOSI VDDA VDD VDD VDD VDDIO Pin No. H1 J7 G9 B9 A4 E2 D5 B4 A3 A2 B3 B2 C6 B7 A8 C7 D6 D4 E3 A7 Signal Name VDDIO VDDIO VDDIO VDDIO VDDIO RD RESET RXD SCK GPIOC1 SS GPIOC0 TCK TDI TDO TMS TRST TXD WR XTAL -
56852 Technical Data, Rev. 8 42 Freescale Semiconductor
Thermal Design Considerations
Part 6 Design Considerations
6.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: TJ = TA + (PD x RJA) Where:
TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RJA = RJC + RCA Where:
RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages:
* * * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple.
56852 Technical Data, Rev. 8 Freescale Semiconductor 43
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
6.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation:
* * Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place six 0.01-0.1F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND. Bypass the VDD and GND layers of the PCB with approximately 100F, preferably with a high-grade capacitor such as a tantalum capacitor. Because the device's output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
* * * * *
*
56852 Technical Data, Rev. 8 44 Freescale Semiconductor
Electrical Design Considerations
* * *
Take special care to minimize noise levels on the VDDA and VSSA pins. When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on.
*
56852 Technical Data, Rev. 8 Freescale Semiconductor 45
Part 7 Ordering Information
Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 7-1 56852 Ordering Information
Part DSP56852 DSP56852 Supply Voltage 1.8-3.3 V 1.8-3.3 V Package Type Mold Array Process Ball Grid Array (MAPBGA) Mold Array Process Ball Grid Array (MAPBGA) Pin Count 81 81 Frequency (MHz) 120 120 Order Number DSP56852VF120 DSP56852VFE *
*This package is RoHS compliant.
56852 Technical Data, Rev. 8 46 Freescale Semiconductor
Electrical Design Considerations
56852 Technical Data, Rev. 8 Freescale Semiconductor 47
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56852 Rev. 8 01/2007

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